There are a number of different types of sensors suitable for use in differential data sensing. FIG. 1 is an example of a latch-based sensor used for sensing differential data. Input PMOS transistors 2,4 are connected respectively between a true signal (BL) and complementary signal (BLB) and a latch circuit 6. The gates of the input transistors 2, 4 each receive a sensor enable signal En which, when applied with logic value 0, allows nodes 8 (INP) and 10 (INN) of the latch circuit 6 to follow the values of the input true signal and complementary signal. An NMOS transistor 12 is connected between a common node 3 of the latch 6 and ground. The gate of the transistor 12 is also connected to receive the enable signal En such that with a logic value 0, transistor 12 is turned off. When enable signal En is logic value 1, transistor 12 will be on and transistors 2, 4 are turned off thereby allowing the latch circuit 6 to operate to pull up one of the outputs 8, 10 and pull down the other output, depending on which input signal is falling with respect to the other one.
The latch circuit 6 comprises PMOS transistor T1 and NMOS transistor T3 connected in series between a supply voltage Vdd and the common node 3. The latch circuit further comprises a pair of transistors including PMOS transistor T2 and NMOS transistor T4 connected in series between the supply voltage Vdd and the common node 3. The gates of the transistors T1 and T3 are connected in common and to junction node INN of the transistors T2 and T4. Similarly, the gates of the transistors T2 and T4 are connected in common and to junction node INP of the transistors T1 and T3. In operation, if we use the sensor circuit 6 for memory read from a memory cell as a sense amplifier, a precharge cycle precharges the bit lines (BL and BLB) to a precharge voltage. The control signal En is kept at a logic low causing the PMOS transistors 2, 4 to conduct and thereby passing on the swing generated by the memory cell to the latch. The sensor control signal En is then transitioned to logic high, causing the ground GND to be connected to the latch circuit 6 via transistor 12. One of the voltages transferred from the input signals (on lines BL and BLB) having a higher value would cause one of the NMOS transistors T3 or T4 to conduct more than the other. The transistor that conducts less will have a higher voltage at the drain terminal in comparison to the other NMOS transistor in the latch circuit 6. As a result, one of transistor T1 or T2 will conduct. Decreasing the rate of fall of the slower transistor further eventually brings it into a linear region of operation. The PMOS itself will move into a cut off region of operation. Then, the junction nodes INP and INN will be placed at two extremes of the supply voltage, i.e., one is pulled up to the supply voltage Vdd and the other is pulled down to the ground GND, depending on the value of the data signals received from the memory cells. This value is fed to an inverter (14 or 16) which works as an output driver for the signal and provides the output. Thus, the cross coupled latch sensor amplifies the true and the complementary data signals by a difference (Vdd-GND), where Vdd is a supply voltage and GND is a ground voltage.
A latch-based sensor circuit has a fast reaction time, e.g. 200 ps, and can be designed against global and local mismatch. The successful operation of the amplifier of FIG. 1 rests on the fact that it is not biased towards the true or complementary signal. In practice, a physical mismatch between the two complementary sides of the differential sensor is inevitable, and can cause the sensor to latch the wrong data due to the offset if an insufficient differential voltage is developed between the input signals. The inputs and outputs need to be carefully isolated: automated placement and routing can lead to unwanted coupling effects.